1. Field of the Invention
The present invention relates to a method of fabricating a stack capacitor of a dynamic random access memory (DRAM) cell, and more particularly to the fabrication of a stack crown capacitor.
2. Description of the Prior Art
A DRAM cell comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor that are built in a semiconductor silicon substrate. There is an electrical contact between the drain of a MOSFET and the bottom storage electrodes of the adjacent capacitor, forming a memory cell of the DRAM device. A large number of memory cells make up the cell arrays which are combined with the peripheral circuit to produce DRAMs.
In recent years, the sizes of the MOSFETs and capacitors have become smaller; thus, the packing densities of these DRAM devices have increased considerably. For example, a number of semiconductor manufacturing companies have already begun mass production of 64 Mbit DRAMs. These high density DRAMs offer the advantages of longer refresh time as well as less power consumption. However, as the sizes of the capacitors become smaller, which the capacitance values of the capacitors are decreasing, which reduces the signal to noise ratio of the DRAM circuits and causes performance problems. The issue of maintaining or even increasing the surface area of the bottom storage electrodes or reducing the thickness of the dielectric layer has become particularly important as the density of the DRAM arrays continues to increase for future generations of memory devices.
There are two ways to deal with this problem: increasing the thickness of the bottom storage electrodes or increasing the surface area of the capacitors. Since increasing the thickness of the bottom storage electrodes is very difficult in terms of precision photolithography and etching process control, increasing the capacitor surface area is an easier approach when the capacitor is used to fabricate 16 Mbit DRAMs and higher. Various shapes of capacitor structures have been used to address this issue. U.S. Pat. No. 5,185,282 to Lee et al. of Hyundai Electronics (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cup-shaped capacitor bottom storage electrodes. Another U.S. Pat. No. 5,021,357 to Taguchi et al. of Fujitsu (the entire disclosure of which is herein incorporated by reference) discloses a method of fabricating fin structure capacitor electrode. U.S. Pat. No. 5,104,821 to Choi et al. of Samsung (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cylinder-shaped (or crown-shaped) capacitor structure. These capacitor structures can effectively increase the capacitance values of the capacitors; however, these processes are too complicated and highly sensitive and therefore impractical in DRAM mass-production.
FIG. 1A illustrates a method of manufacturing a DRAM crown capacitor according to the conventional method, wherein a semiconductor substrate 100 is provided. Using a LOCOS Oxidation process, form a field insulating layer (not shown) on the substrate 100. The field insulating layer isolates each Active Area. Thereafter, using ordinary semiconductor process, such as deposition, photolithography and ion implantation, form the source/drain region 110, the transistor (not shown), the bit line 120 and the first insulating layer 115. The transistor is composed of a gate (not shown) and diffusion areas, such as the source/drain regions 110. The first insulating layer 115 isolates the bit line 120 and the first conductive layer 125 that will be deposited later. In the next step, a first masking layer 122 is formed on the surface of the insulating layer 115. Using a photolithography process and etching steps, pattern the masking layer 122 and the insulating layer 115 to form a contact hole 124 which exposes the surface of the diffusion areas 110. Note, due to the misalignment, a short between the contact hole 124 and the bit line 120 can easily occur in this step. Deposit a first conductive layer 125 on the surface of the first masking layer 122, and conformally fills the contact hole 124. Then, deposit a second insulating layer 130 on the first conductive layer 125.
As shown in FIG. 1B, the second insulating layer 130 is then patterned leaving portions 130a having essentially vertical sidewalls over the contact hole 124. Conventional photolithography procedures and anisotropic etching are used to pattern the second insulating layer 130 to the surface of the first conductive layer 125.
As shown in FIG. 1C, a second conductive layer 140 is then conformally deposited over the first conductive layer 125 and the patterned second insulating layer 130a. As shown in FIG. 1D, the second conductive layer 140 is anisotropically plasma etched back to form first conductive spacers 140a and 140b on the sidewalls of the patterned second insulating layer 130a.
Now, as shown in FIG. 1E, a second masking layer 145 is conformally deposited over the patterned second insulating layer 130a, the first conductive spacers 140a, 140b and the first conductive layer 125.
As shown in FIG. 1F, the second masking layer 145 is anisotropically plasma etched back to form the first insulating spacers 145a and 145b on the sidewalls of the first conductive spacers 140a, 140b.
As shown in FIG. 1G, deposit a third conductive layer 150 over the surface of the first conductive layer 125, the patterned second insulating layer 130a, the first conductive spacers 140a and 140b, and the first insulating spacers 145a and 145b.
As shown in FIG. 1H, the third conductive layer 150 is anisotropically plasma etched back to form the second conductive spacers 150a and 150b on the sidewalls of the first insulating spacers 145a, 145b. The etching is continued to remove the first conductive layer 125 and down to the first masking layer 122 adjacent to a capacitor area 180 to electrically isolate individual bottom electrodes.
Finally, as shown in FIG. 1I, the patterned second insulating layer 130a and the masking spacers 145a, 145b are then selectively removed by etching to form a bottom electrode having a double-crown shape formed from the first conductive spacers 140a and 140b, the second conductive spacers 150a and 150b, and the first conductive layers 125a that electrically connect the diffusion areas 110.
Then, the stacked capacitor is completed by forming a thin capacitor dielectric layer 160 on the bottom electrodes, and forming top electrode comprising a fourth conductive layer 170. Layer 160 is a high-dielectric-constant layer. This layer is typically composed of layers of Si.sub.3 N.sub.4 /SiO.sub.2 (NO), or layers of SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 (ONO). The conventional DRAM crown capacitor manufacturing process is complicated and costly. It includes depositing three conductive layers and two sets of conductive sidewalls spacers to form the bottom storage electrodes. Consequently, the increase of the surface area of the stack crown capacitor is limited. Moreover, in the step of forming a contact hole to expose the surface of the source/drain region, there is no protection between the bit line and the contact hole. When misalignment occurs in photolithography process, the bit line is easily damaged or shorted with the first conductive layer 125 in the contact hole (i.e., the contact plug) when performing the etching process. Then the semiconductor device will easily suffer from data access errors.